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| AZ DISPLAYS, INC. SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY PART NUMBER: DATE: AGM2416B September 13, 2005 Page 1 of 12 AZ DISPLAYS, INC. 1 General Specifications Item Display Pattern Color Module Dimension Viewing Area Active Area Character Size Character Pitch DOT Size DOT Pitch Standard Value Dot-Graphic Mono. 67.0 X 46.8 62.38 X 42.38 / / 0.245 X 0.24 0.265 X 0.26 TN, Positive HTN, Positive STN, Yellow-Green FSTN, Positive Color STN FM LCD Transflective Anti-Glare 6H 12H ST8016 & ST8024 1/160duty, 1/14bias I2C 6800 / / / Build-in o AGM2412B Unit Character with ICON Grayscale FSTN mm mm mm mm mm mm mm TN, Negative HTN, Negative STN, Gray STN, Blue FSTN, Negative Digits Dots 92.0 X 71.8 X 2.0 LCD Type Polarizer Type View Direction LCD Controller & Driver LCD Driving Method Interface Type Backlight Type Backlight Color EL/CCFL Driver type DC-DC Converter Storage Temperature (oC) Transmissive Reflective 4-wire Serial 8080 4-bit 3-wire Serial External (TOPL - T OPH ) (TSTL -- T STH ) C C Operation Temperature ( C) -10 ~ 60 -20 ~ 70 Page 2 of 12 AZ DISPLAYS, INC. 3.1 Pin Description Segment Pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol V0L V12L V34L V5L VSS VSS VDD VDD DBLKB D0 D1 D2 D3 XCK Clock input pin for taking display data * Data is read at the falling edge of the clock pulse. AGM2412B Function Description Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider Ensure that voltages are set such that VSS * * V5 < V43 < V12 < V0. ViL and ViR (i = 0,12, 43, 5) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin Ground Logic power supply Use as contrast control, use PWM signal as input. Connect to VDD for no contrast control. Data bus 15 DOFFB Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (Y1-Y240) are set to level Vss. When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of DISPOFF. When the DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if DISPOFF removal time does not correspond to what is shown in AC characteristics, it can not output the reading data correctly. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Latch pulse input pin for display data Data is latched at the falling edge of the clock pulse. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. Mode selection pin When set to VSS level "L", 8-bit parallel input mode is set. When set to VDD level "H", 4-bit parallel input mode is set. Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Bias power supply pins for LCD drive voltage 16 LP 17 FR 18 MD 19 V5R Page 3 of 12 AZ DISPLAYS, INC. 20 21 22 V34R V12R V0R AGM2412B Normally use the bias voltages set by a resistor divider Ensure that voltages are set such that VSS * * V5 < V43 < V12 < V0. ViL and ViR (i = 0,12, 43, 5) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin Common Pin Pin No. Symbol 23 V0L 24 V12L 25 V34L 26 27 28 29 30 31 32 33 34 VSS VSS VSS VDD VDD VDD EIO2 D7 Function Description Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider. Ensure that voltages are set such that VSS < V43 < V12 < V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage that is assigned by specification for each power pin. Ground Logic power supply Shift data input for shift register at common mode Dual mode data input at common mode Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (Y1-Y160) are set to level Vss. When set to "L, the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. Shift clock pulse input pin for bi-directional shift register * Data is shifted at the falling edge of the clock pulse. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. Bias power supply pins for LCD drive voltage Normally use the bias voltages set by a resistor divider. Ensure that voltages are set such that VSS < V43 < V12 < V0. ViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular voltage that is assigned by specification for each power pin. DOFFB 35 36 LP FR 37 38 39 V34R V12R V0R Page 4 of 12 AZ DISPLAYS, INC. 3.2 Block Diagram AGM2412B Page 5 of 12 AZ DISPLAYS, INC. 4. Electrical-optical Specifications 4.1 Absolute Maximum Ratings AGM2412B 4.2 Electrical-Optical Characteristics No 1 2 3 4 5 6 7 8 9 10 11 Viewing Angle Item Current (all SEG on) Contrast Ratio Threshold voltage Saturation voltage Rise time Response time Fall time On time Off time 6H 12H 3H 9H Frame frequency Symbol Condition I Cr Vth Vsat Tr Tf T ON T OFF *1 * *2 * *3 * ** 4 fM Ta=25oC Cr = 2 o Ta=25 C Ta=25 C Ta=25 C VLCD = 19.5V Ta=25oC Ta=25 C Ta=25 C Ta=25 C Ta=25 C Ta=25 C o o o o o o o Min. 4.5 1.85 45 25 45 45 32 Typ. 15.0 5.0 1.90 2.05 250 200 300 250 64 Max. 30.0 2.10 350 300 450 350 128 Unit *A * V V ms ms ms ms Deg. Deg. Deg. Deg. Hz 4.3 Electrical Characteristics No 1 2 3 4 Item Supply Voltage for Logic Supply Voltage for LCD Driver Supply Current for Logic Frame Frequency Symbol VDD -VSS VDD -VO Ta=25 oC (VLCD) IDD fM Ta=25 C VDD =5.0V Ta=25 C o o Condition Min. 2.5 19.3 - Typ. 19.5 23 80 Max. 5.5 19.7 26 - Unit V V mA Hz Page 6 of 12 AZ DISPLAYS, INC. 5 6 7 8 Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage VIH VIL VOH VOL 0.8X VDD GND VDD-0.4 - AGM2412B VDD 0.2X VDD +0.4 V V V V 4.3 Timming Characteristics * Segment Page 7 of 12 AZ DISPLAYS, INC. 5 6 7 8 Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage VIH VIL VOH VOL 0.8X VDD GND VDD-0.4 - AGM2412B VDD 0.2X VDD +0.4 V V V V 4.3 Timming Characteristics * Segment Page 8 of 12 AZ DISPLAYS, INC. AGM2412B Page 9 of 12 AZ DISPLAYS, INC. AGM2412B Page 10 of 12 AZ DISPLAYS, INC. * Common AGM2412B Page 11 of 12 Page 12 of 12 AZ DISPLAYS, INC. AGM2416B |
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